FIG. 28 is a diagram showing the typical configuration of a PLL circuit and a frequency setting circuit of a gm-C filter circuit (a filter including an OTA and a capacitor is hereinafter referred to as a “gm-C filter”) using the PLL. Conventionally, in the PLL circuit of this type and the frequency setting of a gm-C filter, using the PLL, a gm-C master filter (a second-order gm-C LPF) 111 including an OTA and a capacitor is used as a phase shifter for shifting a phase of 90 degrees, as shown in FIG. 28. An XNOR (exclusive NOR) circuit 115 which receives an input signal to the gm-C master filter 111 and an output signal from the gm-C master filter 111 is used as a phase detector (phase comparator) and a direct current (DC) voltage VCON corresponding to a phase difference between two received signals is obtained through a loop filter (LPF: low-pass filter) 117 receiving an output signal of an inverter 116 that inverts an output signal of the XNOR circuit 115. The signal VCON is used as a control voltage to change the value of the transconductance gm of the OTA. The phase difference of an oscillating frequency from that of a reference frequency fREF is set to 90 degrees, thereby setting the cutoff frequency of a gm-filter circuit (slave filter) 112 to a predetermined value. Each of interface circuits 113 and 114 converts an AC (alternating current) signal to a logic signal (a rectangular wave).
It is assumed that the phase detector (termed also as “phase comparator”) outputs a signal corresponding to the phase difference between two input signals (refer to Non-patent Document 1).
Specifically, if the product of the two input signals is to be output, a multiplier may also be employed as the phase comparator. However, as shown in FIG. 28, the XNOR circuit 115 or an XOR circuit, which are simple digital circuits can be employed.
As described above, in case the phase comparator composed by one of the multiplier, XOR circuit, and XNOR circuit is employed, the simplest phase locked loop (PLL) can be configured. Then, as described in a text book or the like, when the phase difference between the two input signals is 90 degrees (π/2), the loop is pulled in, and locked. When the XOR circuit is used as the phase comparator, for example, and when the phase difference between the two input signals becomes 90 degrees (π/2), the DC voltage of an output signal becomes a VDD/2. Then, the loop is pulled in and locked. At this point, the frequency of the output signal is exactly two times as many as the frequency of the two input signals (with the phases thereof being different to each other by 90 degrees). That is, in the simplest phase locked loop (PLL) in which the XOR circuit is employed as the phase comparator, the phase difference from the reference frequency is just 90 degrees (π/2) at the time of the being locked. As described above, it can be seen that in case that the PLL is configured so that the phase difference becomes 90 degrees, a phase adjusting element such as a differentiator, an integrator, a filter, or the like, by which the phase advancement or delay of 90 degrees is obtained, can be used in addition to a VCO (Voltage Controlled Oscillator) circuit.
FIG. 29 is a diagram showing the configuration of an OTA circuit. As shown in FIG. 28, the OTA circuit includes a transistor M3 operated in a linear operating region in place of source-degeneration resistances of transistors M1 and M2 which constitute a differential pair, and a gate voltage VG of the transistor M3 is adjusted so that the transistor M3 operated in the linear operating region is controlled to equivalently change the source-degeneration resistance, thereby setting the gm (transconductance) value of the OTA variably.
The gm-C master filter circuit 111 including an OTA and a capacitor is a second-order LPF. Then, if there is no insertion loss of the second-order LPF, for simplicity, the transfer characteristic of the second-order LPF becomes one for a DC component. Thus, the transfer characteristic (function) of the second-order LPF is expressed as follows:
                                          H            LPF                    ⁡                      (            s            )                          =                              ω            0            2                                              s              2                        +                                          (                                                      ω                    0                                    Q                                )                            ⁢              s                        +                          ω              0              2                                                          (        1        )            where ω02 indicates a pole frequency and Q indicates a pole-Q value.
FIG. 30 shows the amplitude characteristic of the gm-C master filter circuit 111 with the Q used as a parameter. FIG. 31 shows the phase characteristic of the gm-C master filter circuit 111 with the Q used as the parameter. That is, the gm-C master filter circuit 111 in FIG. 28 generates the phase difference of 0 degrees to −180 degrees, centering on −90 degrees, as a phase shifter. Particularly, the degree of a change becomes large around −90 degrees. Accordingly, the gm-C master filter circuit 111 can be functioned as a −90-degree phase shifter.
On the other hand, the XNOR circuit 115 is used as the phase detector. Though no frequency difference is generated between the reference signal and the output signal of the second-order LPF (phase shifter), the phase difference between them is generated. Thus, the output waveform of the XNOR circuit 115 becomes the rectangular wave, and its duty becomes 50% when the phase difference is 90 degrees. In this case, the rectangular wave has wave height values of a power supply voltage VDD and a ground potential. Thus, the DC voltage component of the output signal of the XNOR circuit 115 (phase detector) becomes the VDD/2. Accordingly, when the loop of the PLL is pulled in, setting is so performed that the output voltage of the loop filter (LPF) is becomes the VDD/2, generally. Alternatively, if a loop gain is to be enhanced, an active PI (proportional+integral) loop filter that uses an OP amplifier for the loop filter (LPF) is configured as shown in FIG. 32, in which the voltage VDD/2 is applied to the plus terminal (non-inverting terminal) of an OP amplifier OP1.
As described above, when the second-order LPF is employed as the phase shifter, the frequency of its output becomes a cutoff frequency when the phase of its output becomes −90 degrees (meaning the delay of the phase by 90 degrees), the amplitude level of its output becomes −3 dB, and the amplitude value of its output is attenuated to 1/√{square root over ( )}2. Accordingly, the cutoff frequency of the second-order LPF (phase shifter) becomes ω0 in the equation (1).
In the Nonpatent Document 1 that is a conventional art, when the second-order LPF constituting the phase shifter is assumed to be a single-input biquad second-order LPF as shown in FIG. 33, the following equation is derived:
                                          V            LPF                                V            in                          =                                                            g                                  m                  ⁢                                                                          ⁢                  1                                            ⁢                              g                                  m                  ⁢                                                                          ⁢                  3                                                                                    C                                  L                  ⁢                                                                          ⁢                  2                                            ⁢                              C                3                                                                        s              2                        +                          s              ⁢                                                          ⁢                                                g                                      m                    ⁢                                                                                  ⁢                    2                                                                    C                  3                                                      +                                                            g                                      m                    ⁢                                                                                  ⁢                    3                                                  ⁢                                  g                                      m                    ⁢                                                                                  ⁢                    4                                                                                                C                                      L                    ⁢                                                                                  ⁢                    2                                                  ⁢                                  C                  3                                                                                        (        2        )            
where
                              ω          0                =                                                            g                                  m                  ⁢                                                                          ⁢                  3                                            ⁢                              g                                  m                  ⁢                                                                          ⁢                  4                                                                                    C                                  L                  ⁢                                                                          ⁢                  2                                            ⁢                              C                3                                                                        (        3        )                                                      ω            0                    Q                =                              g                          m              ⁢                                                          ⁢              2                                            C                          L              ⁢                                                          ⁢              2                                                          (        4        )            
Now, if gm3=gm4=gm and CL2=C2=C hold, the cutoff frequency becomes as follows, using Equation (3).
                              f          CMASTER                =                              g            m                                2            ⁢            π            ⁢                                                  ⁢            C                                              (        5        )            
When gm is assumed to be equal to 1/R and is replaced by an equivalent resistance, the above equation can be expressed as follows:
                              f          CMASTER                =                  1                      2            ⁢            π            ⁢                                                  ⁢            CR                                              (        6        )            Thus, the well known equation of a time constant can be obtained.
By locking fCMASTER to a reference frequency fREF in the PLL, the value of gm/C can be controlled to be constant. That is, when a driving current for each OTA constituting the gm-C filter is set to be equal to a driving current for each OTA constituting the second-order LPF, the gm value of each OTA constituting the gm-C filter and the gm value of each OTA constituting the second-order LPF, which is the phase shifter, can be matched. Then, a constant ratio between each capacitor constituting the gm-C filter and each capacitor constituting the second-order LPF can be expected. Thus, the relationship between the cutoff frequency of the second-order LPF, which is the phase shifter, and the cutoff frequency of the gm-C filter can be controlled to be constant.
Patent Document 1 discloses a configuration that includes a reference filter for receiving a reference signal, a phase comparator for comparing the phase of the output of the reference filter with the phase of the reference signal, a low-pass filter for smoothing the output of the phase comparator, and a comparator for comparing the output of the low-pass filter with a reference voltage. In this configuration, the output signal of the comparator is fed back to the reference filter and a main filter. In the reference filter, the gm or capacitor of the reference filter is changed according to the output of the comparator, and negative feedback is performed so that the phase difference at the frequency of the reference signal becomes 90 degrees.
Further, Patent Document 2 discloses a configuration in which a signal obtained by shifting the phase of an input signal at a reference filter by 90 degrees is supplied to a phase detection circuit. In this configuration, the phase detection circuit detects the phases of the input signal and the signal obtained by shifting the phase of the input signal by 90 degrees. The terminal voltage of a charging capacitor is controlled according to the output of the detection, for supply to a comparator, and then the output of the comparator is negatively fed back to the reference filter.
[Non-Patent Document 1]
V. Gopinathan, Y. P. Tsividis, K. -S. Tan, and R. K. Hester, “Design Considerations for High-Frequency Continuous-Time Filters and Implementation of an Antialising Filter for Digital Video.” IEEE J. Solid-State Circuits, Vol. 25, No. 6, pp. 1368-1378, December 1990.
[Patent Document 1]
JP Patent Kokai Publication No. P2000-209066A (FIG. 3)
[Patent Document 2]
JP Patent No. 2973491 (FIG. 4)